Leaders in Pharmaceutical Business Intelligence (LPBI) Group

Jie Han, PhD, PE – Expert, Author, Writer (EAW): Novel Computational Models for Nanoscale and Biological Applications

 

Roles at LPBI Group:

• Chapter Contributor to

  Volume Two: Latest in Genomics Methodologies for Therapeutics: Gene Editing, NGS & BioInformatics, Simulations and the Genome Ontology

• EAW in the following Research Categories

1. Biological Networks, Gene Regulation and Evolution
2. CANCER BIOLOGY & Innovations in Cancer Therapy
3. Cell Biology, Signaling & Cell Circuits
4. Computational Biology/Systems and Bioinformatics
5. Disease Biology, Small Molecules in Development of Therapeutic Drugs
6. Liver & Digestive Diseases Research
7. Nanotechnology for Drug Delivery
8. Personalized Medicine, Genomic Research & Precision Medicine
9. Statistical Methods for Research Evaluation

• Scientist III: Member of DrugDiscovery @LPBI Group, Drug Delivery Team

https://pharmaceuticalintelligence.com/gama-delta-epsilon-gde-is-a-global-holding-company-absorbing-lpbi/subsidiary-5-joint-ventures-for-ip-development-jvip/drug-discovery-with-3d-bioprinting/anti-cancer-car-t/

BIO

Jie Han, Ph.D., P.Eng.

Associate Professor
Department of Electrical and Computer Engineering
University of Alberta

Edmonton, AB, Canada T6G 2V4

Tel: 780-492-1361 Fax: 780-492-1811

Homepage: http://www.ece.ualberta.ca/~jhan8/

Email: jhan8@ualberta.ca

Identification of Potential Drug Targets in Cancer Signaling Pathways using Stochastic Logical Models

Peican Zhu1,* , Hamidreza Montazeri Aliabadi2,3 , Hasan Uludağ3 & Jie Han1

Zhu, P. et al. Identification of Potential Drug Targets in Cancer Signaling Pathways

using Stochastic Logical Models. Sci. Rep. 6, 23078; doi: 10.1038/srep23078 (2016).

Jie Han’s Nature Article

Brief Biography

Dr. Jie Han received the B.Sc. degree in electronic engineering from Tsinghua University, Beijing, China, in 1999 and the Ph.D. degree from Delft University of Technology, The Netherlands, in 2004.

He is currently an associate professor in the Department of Electrical and Computer Engineering at the University of Alberta. He was a NASA INAC (Institute for Nanoelectronics and Computing) Postdoctoral Fellow in the Department of Electrical and Computer Engineering at the University of Florida from 2004 to 2007. From 2007 to 2009, he worked as a Research Scientist at the Advanced Medical Diagnostics S.A./B.V. in Belgium.

His research interests include approximate computing, stochastic computation, reliability and fault tolerance, nanoelectronic circuits and systems, novel computational models for nanoscale and biological applications. Dr. Jie Han is serving as a guest editor for the Special Issue on Approximate and Stochastic Computing Circuits, Systems and Algorithms, IEEE Transactions on Emerging Topics in Computing, Third Issue, 2016. He is serving as a Technical Program Chair in the IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI 2016). He served as a General Chair and a Technical Program Chair in the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) 2013 and 2012, respectively. He also served as a Technical Program Committee Member in the Design, Automation & Test in Europe Conference (DATE 2014, 2015 and 2016), the 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2014), the 26th IEEE International System-on-Chip Conference (SOCC 2013), DFT 2011-2015, the International Workshop on Unique Chips and Systems, 2010 (UCAS-6) and 2012 (UCAS-7), and the First International Workshop on Secure and Resilient Architecture and Systems (WSRAS 2012).

Dr. Han and coauthors have won the Best Paper Award at IEEE/ACM International Symposium on Nanoscale Architectures 2015 (NanoArch’15) and a Best Paper Nomination at the 25th IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI’15). He was nominated for the 2006 Christiaan Huygens Prize of Science by the Royal Dutch Academy of Science (Koninklijke Nederlandse Akademie van Wetenschappen (KNAW) Christiaan Huygens Wetenschapsprijs). His work was recognized by the 125th anniversary issue of Science, for developing theory of fault-tolerant nanocircuits. He is a senior member of the Institute of Electrical and Electronics Engineers (IEEE) and the American Society for Engineering Education (ASEE).

 

EDUCATION

• D., Delft University of Technology, The Netherlands, 2004.

Dissertation: Fault-Tolerant Architectures for Nanoelectronic and Quantum Devices

• Sc., Electronic Engineering, Tsinghua University, Beijing, China, 1999.

RESEARCH INTEREST

Approximate computing, stochastic computation, reliability, fault tolerance and energy efficiency in nanoelectronic circuits and systems, novel computational models for nanoscale and biological applications.

RESEARCH EXPERIENCE

• July 2015 – present, Associate Professor, Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Alberta, Canada.
• July 2009 – June 2015, Assistant Professor, Department of Electrical and Computer Engineering, University of Alberta, Edmonton, Alberta, Canada.
• June 2007 – June 2009, Research Scientist, Advanced Medical Diagnostics S.A./B.V., Waterloo, Belgium.
• August 2004 – May 2007, Postdoctoral Fellow, Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL, USA.
• March 2001 – May 2001, Visiting Researcher, University College London, London, UK.
• November 1999 – August 2004, Research Assistant, Department of Applied Physics, Delft University of Technology, The Netherlands.

HONORS AND AWARDS

• Best Paper Award: IEEE/ACM International Symposium on Nanoscale Architectures 2015 (NanoArch’15).
• Best Paper Nomination: The 25th IEEE/ACM Great Lakes Symposium on VLSI 2015 (GLSVLSI’15).
• Nominated for the 2006 Christiaan Huygens Prize of Science by the Royal Dutch Academy of Science (Koninklijke Nederlandse Akademie van Wetenschappen (KNAW) Christiaan Huygens Wetenschapsprijs).
• Named in “Milestones of Science” for 2003 by the 125th anniversary issue of Science (July 1, 2005, Vol. 309, No. 5731), for developing theory of fault-tolerant nanocircuits.

PROFESSIONAL SERVICE

Editorial Board Member:

• Advisory Board Member of OA Biology (a journal by Open Access Publishing London, UK).

Guest Editor

• Joint Special Section on VLSI and Nanotechnology Design Trends for Computing Innovations, IEEE Transactions on Nanotechnology & IEEE Transactions on Emerging Topics in Computing, September 2017
• Special Section on Approximate and Stochastic Computing Circuits, Systems and Algorithms, IEEE Transactions on Emerging Topics in Computing, Third Issue, 2016.

General Chair

• IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2013), October 2-4, 2013, New York City, NY, USA.

Technical Program Committee Chair

• IEEE/ACM Great Lakes Symposium on VLSI (GLSVLSI 2016), Boston, MA, USA, May 18 – 20, 2016.
• IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012), October 3-5, 2012, Austin, Texas, USA.

Finance Chair

• IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2015 and 2016.

Technical Program Committee Member

• Design, Automation & Test in Europe (DATE 2016, 2015 and 2014).
• IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2011, 2014, 2015 and 2016).
• The 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems (VLSI-Design 2016), Kolkata, West Bengal, India, January 4-8, 2016.
• The 22nd IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2014), Playa del Carmen, Mexico, October 6-8, 2014.
• The 26th IEEE International System-on-Chip Conference (SOCC 2013), Erlangen, Germany, September 4 – 6, 2013.
• International Workshop on Unique Chips and Systems, Atlanta, Georgia, USA, 2010 (UCAS-6), and New Orleans, Louisiana, USA, 2012 (UCAS-7).
• The First International Workshop on Secure and Resilient Architecture and Systems (WSRAS 2012), Minneapolis, MN, USA, September 19, 2012.

GRADUATE STUDENT SUPERVISION

Current:

1. Mohammad Saeed Ansari (Ph.D., 2015 – present, co-advised by Prof. Bruce Cockburn and Recipient of University of Alberta Doctoral Recruitment Scholarship)
2. Siting Liu (Ph.D., 2014 – present)
3. Yidong Liu (Ph.D., 2014 – present, Recipient of University of Alberta Doctoral Recruitment Scholarship)
4. Honglan Jiang (Ph.D., 2013 – present)
5. Anqi Jing (MSc, 2015 – present, Recipient of University of Alberta Master’s Recruitment Scholarship)
6. Yuanzhuo Qu (MSc, 2015 – present, co-advised by Prof. Witold Pedrycz)
7. Oleg Oleynikov (MSc, 2015 – present, co-advised by Prof. Bruce Cockburn)

Graduated:

1. Hao Chen (M.Sc., January 2012, currently at PMC Sierra, Vancouver, BC)
2. Eugene Leung (M.Eng., April 2012)
3. Jinghang Liang (M.Sc., August 2012, Recipient of an Alberta Innovates Graduate Student Scholarship)
4. Cong Liu (M.Sc., August 2014, Recipient of an Alberta Innovates Graduate Student Scholarship)
5. Michael Shoniker (M.Sc., April 2015, co-advised by Prof. Bruce Cockburn, Recipient of Queen Elizabeth II Master’s Scholarship)
6. Ran Wang (M.Sc., June 2015, co-advised by Prof. Bruce Cockburn)
7. Peican Zhu (Ph.D., August 2015, Recipient of an Alberta Innovates Graduate Student Scholarship)

 

UNDERGRADUATE/GRADUATE INTERN STUDENT SUPERVISION

1. Gautam Kamath (MITACS Summer Intern Student, 2011)
2. Ajaypat Jain (MITACS Summer Intern Student, 2012)
3. Michael Shoniker (U of A undergraduate student, 2012)
4. Jaap Donker (A visiting M.Sc. student from Delft University of Technology, The Netherlands, 2012)
5. Rodrigo Cavalcanti (MITACS Summer Intern Student, 2013)
6. Yu Ren (UARE Summer Intern Student, 2013)
7. Ashutosh Pandey (MITACS Summer Intern Student, 2014)
8. Naman Maheshwari (MITACS Summer Intern Student, 2014)
9. Chen Zou (UARE Summer Intern Student, 2014)
10. Oleg Oleynikov (U of A undergraduate student, 2015)
11. Sudarsan Mahendran (MITACS Summer Intern Student, 2015)
12. Chengkun Shen (UARE Summer Intern Student, 2015)
13. Lantao Mei (U of A Dean’s Research Award, 2013)
14. Lu Tong (U of A Dean’s Research Award, 2015)
15. Xuefei Han (U of A Dean’s Research Award, 2015)
16. Yiyang Fu (U of A Dean’s Research Award, 2015, 2016)
17. Xinru Song (U of A Dean’s Research Award, 2016)
18. Chenjin Lu (U of A Dean’s Research Award, 2016)

TEACHING

• ECE412 Fault-tolerant computing
• ECE410 Advanced Digital Logic Design
• ECE511 Digital ASIC Design
• ECE750 Advanced Topics in Micro and NanoSystems

DEPARTMENT SERVICE

• Selection Committee, Department OF Electrical and Computer Engineering, University of Alberta, 2016 – present
• Publicity Committee, Department OF Electrical and Computer Engineering, University of Alberta, 2010 – 2015 (Chair 2014 – 2015)

PUBLICATIONS

Books and Book Chapters

1. Peican Zhu, Jinghang Liang and Jie Han, “Toward Intracellular Delivery and Drug Discovery: Stochastic Logic Networks as Efficient Computational Models for Gene Regulatory Networks,” a chapter inIntracellular Delivery II, Fundamental Biomedical Technologies, Volume 7, 2014, pp 327-359. Springer Netherlands: Dordrecht.
2. Jie Han and José A.B. Fortes, “Reliability Analysis of Computational Structures using Nanotechnology-based Majority Logic,” a chapter in Dekker Encyclopedia of Nanoscience and Nanotechnology, Second Edition. Taylor and Francis: New York, Published online: 25 Jun 2012; 1-9.
3. Jie Han and Hao Chen, “Variation-induced Error Rate (ViER) and Variability-aware Soft Error Rate (VaSER) Analyses for Advanced CMOS Technology,” a chapter in Horizons in Computer Science Research, Volume 5, August 2012, Nova Science Publishers.
4. Jie Han and Pieter Jonker, “Computing with Superconducting Circuits of Josephson Junctions,” Chapter 6 in Nanophysics, Nanoclusters and Nanodevices, 2007, Nova Science Publishers, 183-218. ISBN: 1-59454-852-8. Also in Superconductivity and Superconducting Wires (Horizons in World Physics, Volume 267), 2010. ISBN: 978-1-60876-226-2.
5. Jie Han, Fault-Tolerant Architectures for Nanoelectronic and Quantum Devices, Universal Press, Veenendaal, The Netherlands, 2004. A Ph.D. dissertation of the Delft University of Technology, 1-135. ISBN: 90-9018888-6.

Refereed Journal Articles (with Student Names in Bold)

1. Peican Zhu, Hamidreza Montazeri Aliabadi, Hasan Uludag, and Jie Han, “Identification of Potential Drug Targets in Cancer Signaling Pathway using Stochastic Logical Models,” Scientific Report, 6, 23078; doi: 10.1038/srep23078 (2016).
2. Peican Zhu, Jie Han, Leibo Liu and Fabrizio Lombardi, “Reliability Evaluation of Phased-Mission Systems Using Stochastic Computation,” IEEE Transactions on Reliability, accepted for publication, 2016.
3. Ran Wang, Jie Han, Bruce Cockburn and Duncan Elliott, “Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures,” IEEE Transactions on VLSI Systems, accepted for publication, 2016.
4. Ran Wang, Jie Han, Bruce Cockburn and Duncan Elliott, “Design, Evaluation and Fault-Tolerance Analysis of Stochastic FIR Filters,” Microelectronics Reliability, vol. 57, pp. 111 – 127, February 2016.
5. Peican Zhu, Jie Han, Yangming Guo and Fabrizio Lombardi, “Reliability and Criticality Analysis of Communication Networks by Stochastic Computation,” IEEE Network, to appear, 2015.
6. Pilin Junsangsri, Jie Han and Fabrizio Lombardi, “Circuits for a Perpendicular Magnetic Anisotropic (PMA) Racetrack Memory,” IEEE Transactions on Multi-Scale Computing Systems, vol. 1, no. 3, pp. 127 – 137, 2015.
7. Jie Han, “Computing: Naturally random,” Nature Nanotechnology 10, 1011–1012 (2015) | doi:10.1038/nnano.2015.215.
8. Linbin Chen, Jie Han, Weiqiang Liu and Fabrizio Lombardi, “On the Design of Approximate Restoring Dividers for Error-Tolerant Applications,” accepted for publication in IEEE Transactions on Computers (on October 11, 2015).
9. Honglan Jiang, Jie Han, Fei Qiao and Fabrizio Lombardi, “Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation,” accepted for publication in IEEE Transactions on Computers (on October 8, 2015).
10. Pilin Junsangsri, Jie Han and Fabrizio Lombardi, “Design of a Hybrid Non-Volatile SRAM Cell for Concurrent SEU Detection and Correction,” Integration, the VLSI Journal, vol. 52, pp. 156-167, January 2016.
11. Chen Wu, Chenchen Deng, Leibo Liu, Jie Han, Jiqiang Chen, Shouyi Yin, and Shaojun Wei, “An Efficient Application Mapping Approach for the Co-Optimization of Reliability, Energy and Performance in Reconfigurable NoC Architectures,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, no. 8, pp. 1264 – 1277, 2015.
12. Pilin Junsangsri, Jie Han and Fabrizio Lombardi, “Logic-in-Memory (LiM) with a Non-Volatile Programmable Metallization Cell (PMC),” accepted for publication in IEEE Transactions on VLSI Systems (on February 25, 2015).
13. Chen Wu, Chenchen Deng, Leibo Liu, Shouyi Yin, Jie Han, and Shaojun Wei, “Reliability-aware mapping for various NoC topologies and routing algorithms under performance constraints,” Science China Information Sciences, Vol. 58, 082401:1–082401:14, August 2015.
14. Ke Chen, Jie Han and Fabrizio Lombardi, “On the Restore Operation in MTJ-Based Non Volatile SRAM Cells,” IEEE Transactions on VLSI Systems, vol. 23, no. 11, pp. 2695 – 2699, 2015.
15. Leibo Liu, Chen Wu, Chenchen Deng, Shouyi Yin, Qinghua Wu, Jie Han, and Shaojun Wei, “A Flexible Energy- and Reliability-Aware Application Mapping for NoC-based Reconfigurable Architectures,” IEEE Transactions on VLSI Systems, vol. 23, no. 11, pp. 2566 – 2580, 2015.
16. Yu Ren, Leibo Liu, Shouyi Yin, Jie Han, and Shaojun Wei, “Efficient Fault-Tolerant Topology Reconfiguration Using a Maximum Flow Algorithm,” ACM Transactions on Reconfigurable Technology and Systems, Vol. 8, No. 3, May 2015. Article No. 19.
17. Peican Zhu, Jie Han, Leibo Liu and Fabrizio Lombardi, “A Stochastic Approach for the Analysis of Dynamic Fault Trees with Spare Gates under Probabilistic Common Cause Failures,” IEEE Transactions on Reliability, vol. 64, no. 3, pp. 878 – 892, 2015.
18. Jie Han, Eugene Leung, Leibo Liu and Fabrizio Lombardi, “A Fault-Tolerant Technique using Quadded Logic and Quadded Transistors,” IEEE Transactions on VLSI Systems, vol. 23, no. 8, pp. 1562 – 1566, 2015.
19. Wei Wei, Kazuteru Namba, Jie Han and Fabrizio Lombardi, “Design of a Non-Volatile 7T1R SRAM Cell for Instant-on Operation,” IEEE Transactions on Nanotechnology, vol. 13, no. 5, pp. 905 – 916, 2014.
20. Ke Chen, Jie Han, and Fabrizio Lombardi, “On the non-volatile performance of Flip-Flop/SRAM cells with a single MTJ,” IEEE Transactions on VLSI Systems, vol. 23, no. 6, pp. 1160 – 1164, 2015.
21. Peican Zhu, Jinghang Liang and Jie Han, “Gene Perturbation and Intervention in Context-Sensitive Stochastic Boolean Networks,” BMC Systems Biology 2014, 8:60. (Among top eight highly accessed articles in the past 30 days since its publication)
22. Peican Zhu and Jie Han, “Asynchronous Stochastic Boolean Networks as Gene Network Models,” Journal of Computational Biology, 21(10): 760-770, October 2014.
23. Jinghang Liang, Linbin Chen, Jie Han and Fabrizio Lombardi, “Design and Evaluation of Multiple Valued Logic Gates using Pseudo N-type Carbon Nanotube FETs,” IEEE Transactions on Nanotechnology, vol. 13, no. 4, pp. 695-708, 2014.
24. Cong Liu, Jie Han and Fabrizio Lombardi, “An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders,” IEEE Transactions on Computers, vol. 64, no. 5, pp. 1268 – 1281, 2015.
25. Wei Wei, Jie Han and Fabrizio Lombardi, “Robust HSPICE Modeling of a Single Electron Turnstile,” Microelectronics Journal (Elsevier), vol. 45, no. 4, pp. 394-407, April 2014.
26. Amir Momeni, Jie Han, Paolo Montuschi and Fabrizio Lombardi, “Design and Analysis of Approximate Compressors for Multiplication,” IEEE Transactions on Computers, vol. 64, no. 4, pp. 984 – 994, 2015.
27. Peican Zhu, Jie Han, Leibo Liu and Ming J. Zuo, “A Stochastic Approach for the Analysis of Fault Trees with Priority AND Gates,” IEEE Transactions on Reliability, 63, no. 2, pp. 480 – 494, June 2014.
28. Peican Zhu and Jie Han, “Stochastic Multiple-Valued Gene Networks,” IEEE Transactions on Biomedical Circuits and Systems, 8, no. 1, pp. 42 – 53, 2014.
29. Yu Ren, Leibo Liu, Shouyi Yin, Jie Han, Qinghua Wu and Shaojun Wei, “Fault Tolerant NoC Architecture Using Quad-Spare Mesh Topology and Dynamic Reconfiguration,” Journal of Systems Architecture (Elsevier), Vol. 59, No. 7, pp. 482 – 491, 2013.
30. Wei Wei, Jie Han and Fabrizio Lombardi, “Design and Evaluation of a Hybrid Memory Cell by Single-Electron Transfer,” IEEE Transactions on Nanotechnology, Vol. 12, No. 1, pp. 57-70, 2013.
31. Jie Han, Hao Chen, Jinghang Liang, Peican Zhu, Zhixi Yang and Fabrizio Lombardi, “A Stochastic Computational Approach for Accurate and Efficient Reliability Evaluation,” IEEE Transactions on Computers, 63, no. 6, pp. 1336 – 1350, 2014.
32. Jinghang Liang and Jie Han, “Stochastic Boolean Networks: An Efficient Approach to Modeling Gene Regulatory Networks,” BMC Systems Biology (Impact factor: 3.15), 6:113, 2012.(Among top three highly accessed articles in the past 30 days since its publication)
33. Jinghang Liang, Jie Han and Fabrizio Lombardi, “Analysis of Error Masking and Restoring Properties of Sequential Circuits,” IEEE Transactions on Computers, 62, no. 9, pp. 1694 – 1704, 2013.
34. Jinghang Liang, Jie Han and Fabrizio Lombardi, “New Metrics for the Reliability of Approximate and Probabilistic Adders,” IEEE Transactions on Computers, 62, no. 9, pp. 1760 – 1771, 2013.
35. Jinghang Liang, Zhiyin Zhou, Jie Han and Duncan G. Elliott, “A 6.0-13.5 GHz Alias-Locked Loop Frequency Synthesizer in 130 nm CMOS,” IEEE Transactions on Circuits and Systems I: Regular Papers, 60, no. 1, pp. 108 – 115, 2013.
36. Jie Han, Erin Boykin, Hao Chen, Jinghang Liang and Jose A.B. Fortes, “On the Reliability of Computational Structures using Majority Logic,” IEEE Transactions on Nanotechnology, 10, no. 5, pp. 1099-1112, September 2011.
37. Jie Han, Hao Chen, Erin Boykin and Jose A.B. Fortes, “Reliability Evaluation of Logic Circuits using Probabilistic Gate Models,” Microelectronics Reliability (Elsevier), vol. 51, no. 2, pp. 468-476, 2011.
38. Jie Han, Jianbo Gao, Yan Qi, Pieter Jonker and Jose A.B. Fortes. “Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics,” IEEE Design and Test of Computers, vol. 22, no. 4, pp. 328-339, July/August 2005.
39. Jie Han and Pieter Jonker, “A Defect- and Fault-Tolerant Architecture for Nanocomputers,” Nanotechnology, vol. 14, no. 2, pp. 224-230, 2003.
40. Jie Han and Pieter Jonker, “A System Architecture Solution for Unreliable Nanoelectronic Devices,” IEEE Transactions on Nanotechnology, vol. 1, no. 4, pp. 201-208, December 2002.

Refereed Conference Articles

1. Chen Zou, Weikang Qian and Jie Han, “DPALS: A Dynamic Programming-based Algorithm for Two-level Approximate Logic Synthesis,” in The 11th International Conference on ASIC (ASICON 2015), Chengdu, China, 2015.
2. Zhixi Yang, Jie Han and Fabrizio Lombardi, “Approximate Compressors for Error-Resilient Multiplier Design,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2015), Amherst, MA, USA, 2015.
3. Salin Junsangsri, Fabrizio Lombardi and Jie Han, “Evaluating the Impact of Spike and Flicker Noise in Phase Change Memories,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2015), Amherst, MA, USA, 2015.
4. Pilin Junsangsri, Fabrizio Lombardi and Jie Han, “HSPICE Macromodel of a PMA Racetrack Memory,” in 2015 IEEE Nanotechnology Materials and Devices Conference (NMDC), Anchorage, Alaska, USA, September 13-16th, 2015.
5. Ran Wang, Jie Han, Bruce Cockburn and Duncan Elliott, “Design and Evaluation of Stochastic FIR Filters,” in  2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, Victoria, BC, Canada, August 24 – 26, 2015.
6. Ran Wang, Jie Han, Bruce Cockburn and Duncan Elliott, “Stochastic Circuit Design and Performance Evaluation of Vector Quantization,” in  IEEE ASAP 2015, IEEE 26th International Conference on Application-specific Systems, Architectures and Processors, Toronto, Canada, July 27 – 29, 2015.
7. Zhixi Yang, Jie Han and Fabrizio Lombardi, “Transmission Gate-based Approximate Adders for Inexact Computing,” IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch’15), Boston, MA, U.S.A., July 8-10, 2015. (Best Paper Award)
8. Ke Chen, Fabrizio Lombardi and Jie Han, “Matrix Multiplication by an Inexact Systolic Array,” IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch’15), Boston, MA, U.S.A., July 8-10, 2015.
9. Honglan Jiang, Jie Han and Fabrizio Lombardi, “A Comparative Review and Evaluation of Approximate Adders,” in GLSVLSI’15, Proceedings of the 25th IEEE/ACM Great Lakes Symposium on VLSI, Pittsburgh, PA, USA, 2015.
10. Linbin Chen, Jie Han, Weiqiang Liu and Fabrizio Lombardi, “Design of Approximate Unsigned Integer Non-restoring Divider for Inexact Computing,” in GLSVLSI’15, Proceedings of the 25th IEEE/ACM Great Lakes Symposium on VLSI, Pittsburgh, PA, USA, 2015. (Best Paper Nomination – Top 4/148)
11. Pilin Junsangsri, Fabrizio Lombardi and Jie Han, “A Ternary Content Addressable Cell Using a Single Phase Change Memory (PCM),” in GLSVLSI’15, Proceedings of the 25th IEEE/ACM Great Lakes Symposium on VLSI, Pittsburgh, PA, USA, 2015.
12. Michael Shoniker, Bruce F. Cockburn, Jie Han and Witold Pedrycz, “Minimizing the Number of Process Corner Simulations during Design Verification,” Design, Automation & Test in Europe Conference (DATE 2015), Grenoble, France, March 9 – 13, 2015.
13. Ke Chen, Fabrizio Lombardi and Jie Han, “An Approximate Voting Scheme for Reliable Computing,” Design, Automation & Test in Europe Conference (DATE 2015), Grenoble, France, March 9 – 13, 2015.
14. Naman Maheshwari, Zhixi Yang, Jie Han, and Fabrizio Lombardi, “A Design Approach for Compressor Based Approximate Multipliers,” in International Conference on VLSI Design and Embedded Systems (VLSID 2015), Bangalore, India, January 3 – 7, 2015.
15. Leibo Liu, Yu Ren, Chenchen Deng, Shouyi Yin, Shaojun Wei, and Jie Han, “A Novel Approach Using a Minimum Cost Maximum Flow Algorithm for Fault-Tolerant Topology Reconfiguration in NoC Architectures,” in the 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), Chiba/Tokyo, Japan, 2015.
16. Pilin Junsangsri, Jie Han and Fabrizio Lombardi, “A System-level Scheme for Resistance Drift Tolerance of a Multilevel Phase Change Memory,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2014), Amsterdam, The Netherlands, 2014.
17. Linbin Chen, Fabrizio Lombardi and Jie Han, “FDSOI SRAM Cells for Low Power Design at 22nm Technology Node,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), College Station, Texas, USA, August 3-6, 2014. pp. 527-530.
18. Linbin Chen, Fabrizio Lombardi and Jie Han, “An Enhanced HSPICE Macromodel of a PCM Cell with Threshold Switching and Recovery Behavior,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), College Station, Texas, USA, August 3-6, 2014. pp. 993-996.
19. Pilin Junsangsri, Fabrizio Lombardi and Jie Han, “A Memristor-based TCAM (Ternary Content Addressable Memory) Cell,” IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch’14), Paris, France, July 8-10, 2014. pp. 1-6.
20. Pilin Junsangsri, Fabrizio Lombardi and Jie Han, “HSPICE Macromodel of a Programmable Metallization Cell (PMC) and its Application to Memory Design,” IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch’14), Paris, France, July 8-10, 2014. pp. 45-50.
21. Pilin Junsangsri, Jie Han and Fabrizio Lombardi, “A Memristor-Based Memory Cell with No Refresh,” IEEE International Conference on Nanotechnology, Toronto, Canada, August 18-21, 2014.
22. Cong Liu, Jie Han and Fabrizio Lombardi, “A Low-Power, High-Performance Approximate Multiplier with Configurable Partial Error Recovery,” Design, Automation & Test in Europe (DATE 2014), Dresten, Germany, March 24 – 28, 2014.
23. Pilin Junsangsri, Fabrizio Lombardi and Jie Han, “A Hybrid Non-Volatile SRAM Cell with Concurrent SEU Detection and Correction,” Design, Automation & Test in Europe (DATE 2014), Dresten, Germany, March 24 – 28, 2014.
24. Hao Wu, Jie Han and Fabrizio Lombardi, “A PCM-based TCAM cell using NDR,” IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch’13), New York City, USA, July 15-17, 2013.
25. Zhixi Yang, Ajaypat Jain, Jinghang Liang, Jie Han and Fabrizio Lombardi, “Approximate XOR/XNOR-based Adders for Inexact Computing,” IEEE International Conference on Nanotechnology, Beijing, China, August 5-8, 2013.
26. Ke Chen, Jie Han and Fabrizio Lombardi, “Design and Evaluation of two MTJ-Based Content Addressable Non-Volatile Memory Cells,” IEEE International Conference on Nanotechnology, Beijing, China, August 5-8, 2013.
27. Pilin Junsangsri, Jie Han and Fabrizio Lombardi, “On the Drift Behaviors of a Phase Change Memory (PCM) Cell,” IEEE International Conference on Nanotechnology, Beijing, China, August 5-8, 2013.
28. Jie Han and Michael Orshansky, “Approximate Computing: An Emerging Paradigm For Energy-Efficient Design,” in ETS’13, Proceedings of the 18th IEEE European Test Symposium, Avignon, France, May 27-31, 2013.
29. Yu Ren, Leibo Liu, Shouyi Yin, Qinghua Wu, Shaojun Wei and Jie Han, “A VLSI Architecture for Enhancing the Fault Tolerance of NoC using Quad-spare Mesh Topology and Dynamic Reconfiguration,” in IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 2013.
30. Jianping Gong, Jie Han, Yong-Bin Kim and Fabrizio Lombardi, “Hardening a Memory Cell for Low Power Operation by Gate Leakage Reduction,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2012), Austin, Texas, USA, pp. 73-78, 2012.
31. Jinghang Liang, Linbin Chen, Jie Han and Fabrizio Lombardi, “Design and Reliability Analysis of Multiple Valued Logic Gates using Carbon Nanotube FETs,” in IEEE/ACM International Symposium on Nanoscale Architectures, Amsterdam, The Netherlands, pp. 131-138, 2012.
32. Pilin Junsangsri, Jie Han and Fabrizio Lombardi, “Macromodeling a Phase Change Memory (PCM) Cell by HSPICE,” in IEEE/ACM International Symposium on Nanoscale Architectures, Amsterdam, The Netherlands, pp. 77-84, 2012.
33. Vikas Sakode, Jie Han and Fabrizio Lombardi, “Cell Design and Comparative Evaluation of a 1T Memristor-Based Memory,” in IEEE/ACM International Symposium on Nanoscale Architectures, Amsterdam, The Netherlands, pp. 152-159, 2012.
34. Wei Wei, Jie Han and Fabrizio Lombardi, “Modeling a Single Electron Turnstile in HSPICE,” in GLSVLSI’12, Proceedings of the 22th IEEE/ACM Great Lakes Symposium on VLSI, Salt Lake City, Utah, USA, pp. 221-226, 2012.
35. Jinghang Liang, Jie Han and Fabrizio Lombardi, “On the Reliable Performance of Sequential Adders for Soft Computing,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2011), Vancouver, BC, Canada, pp. 3-10, 2011.
36. Hao Chen, Jie Han and Fabrizio Lombardi, “A Transistor-Level Stochastic Approach for Evaluating the Reliability of Digital Nanometric CMOS Circuits,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2011), Vancouver, BC, Canada, pp. 60-67, 2011.
37. Rajderkar, M. Ottavi, S. Pontarelli, J. Han and F. Lombardi, “On the Effects of Intra-Gate Resistive Open Defects in Gates at Nanoscale CMOS,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2011), Vancouver, BC, Canada, 2011.
38. Wei Wei, Jie Han and Fabrizio Lombardi, “A Hybrid Memory Cell Using Single-Electron Transfer,” Proc. IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH’11), San Diego, CA, USA, pp. 16–23, 2011.
39. Xiaojun Ma, Masoud Hashempour, Jie Han and Fabrizio Lombardi, “Modeling errors in synthesized tile sets for template manufacturing by DNA self-assembly,” in IEEE Conference on Nanotechnology (IEEE-Nano), Portland, Oregon, USA, pp. 1707–1712, 2011.
40. Hao Chen and Jie Han, “Stochastic Computational Models for Accurate Reliability Evaluation of Logic Circuits,” in GLSVLSI 2010, Proceedings of the 20th IEEE/ACM Great Lakes Symposium on VLSI, Providence, Rhode Island, USA, pp. 61–66.
41. Erin Taylor, Jie Han and Jose Fortes, “An Investigation into the Maximum Tolerable Error Rate of Majority Gates for Reliable Computation,” IEEE International Workshop on Defect and Fault Tolerant Nanoscale Architectures (NANOARCH), 2006.
42. Erin Taylor, Jie Han and Jose Fortes, “Towards Accurate and Efficient Reliability Modeling of Nanoelectronic Circuits,” in Proc. IEEE-NANO 2006, IEEE Conference on Nanotechnology, vol. 1, pp. 395-398.
43. Jie Han, Erin Taylor, Jianbo Gao and Jose Fortes, “Faults, Error Bounds and Reliability of Nanoelectronic Circuits,” in Proc. IEEE ASAP 2005, IEEE 16th International Conference on Application-specific Systems, Architectures and Processors, pp. 247-253.
44. Jie Han, Erin Taylor, Jianbo Gao and Jose Fortes, “Reliability Modeling of Nanoelectronic Circuits,” in Proc. IEEE-NANO 2005, IEEE Conference on Nanotechnology, pp. 104-107.
45. Jie Han and Pieter Jonker, “From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers,” in Proc. 17th Int. Conf. on Pattern Recognition (ICPR17), 2004, Vol. 3, pp. 2-7.
46. Jie Han and Pieter Jonker, “A Study on Fault-Tolerant Circuits using Redundancy,” in Proc. VLSI 2003, Multiconference in Computer Science and Engineering, pp. 65-69.
47. Jie Han and Pieter Jonker, “Quantum Cellular Nonlinear Networks using Josephson Circuits,” in Proc. IEEE-NANO 2003, IEEE Conference on Nanotechnology, pp. 457-460.
48. Jie Han and Pieter Jonker, “On Quantum Computing with Macroscopic Josephson Qubits,” in Proc. IEEE-NANO 2002, IEEE Conference on Nanotechnology, pp. 305-308.
49. Jie Han and Pieter Jonker, “Novel Computing Architectures on Arrays of Josephson Persistent Current Bits,” in Proc. MSM 2002, Fifth International Conference on Modeling and Simulation of Microsystems, pp. 636-639.
50. Jie Han and Pieter Jonker, “A Fault-Tolerant Technique for Nanocomputers: NAND Multiplexing,” in Proc. 8th Annual Conf. of the Advanced School for Computing and Imaging, 2002, pp. 59-66.
51. Pieter Jonker and Jie Han, “On Quantum and Classical Computing with Arrays of Superconducting Persistent Current Qubits,” in Proc. CAMP2000, Fifth IEEE International Workshop on Computer Architectures for Machine Perception, pp. 69-78, 2000.

 

REPORTS

1. Mike Forshaw, David Crawley, Pieter Jonker, Jie Han, and C. Sotomayor Torres, “Nano_Arch_Review: A Review of the Status of Research and Training into Architectures for Nanoelectronic and Nanophotonic Systems in the European Research Area,” EU 6th Framework Programme Report, University College, London, UK, 2004, July, 1-36.

 

INVITED TALKS

• “A Comparative Study of Approximate Adders and Multipliers” at the Workshop on Approximate Computing, University of Paderborn, Paderborn, Germany, October 2015. (Hosted by Profs. Sybille Hellebrand and Peter Schreier)
• “Stochastic and Approximate Computing: Toward Fault-tolerant and Energy-efficient Processors for Robot Brains?” at the Faculty of Mechanical, Maritime and Materials Engineering, Delft University of Technology, Delft, The Netherlands, May 2013. (Hosted by Prof. dr. ir. Pieter Jonker)
• “New Design Metrics for the Reliability of Approximate and Probabilistic Adders,” at the Department of Electrical and Computer Engineering, University of Texas, Austin, USA, October 2012. (Hosted by Prof. Michael Orshansky)
• “Stochastic Computational Models for Accurate Reliability Evaluation of Logic Circuits,” at Dagstuhl Seminar on “Verifying Reliability” (as the only invitee from Canada), Germany, August 2012.
• “Stochastic Computational Models for Accurate Reliability Evaluation of Logic Circuits,” at the Institute of Software, Tsinghua University, Beijing, China, May 2012. (Hosted by Prof. Dong Xiang)
• “Stochastic Computational Models for Accurate Reliability Evaluation of Logic Circuits,” at the Institute of Microelectronics, Tsinghua University, Beijing, China, August 2010. (Hosted by Prof. Leibo Liu)

 

INDUSTRY R&D CONTRIBUTIONS

Developed tissue characterization algorithms and implemented the algorithms in software for the diagnostics of prostate, thyroid and breast cancers. The algorithms, based on Fourier and wavelet transforms, were developed for use with the data of ultrasonic imaging. The algorithms were tested in clinical studies and were successfully implemented in the first commercial product of its kind, the prostate Histoscanning™, for the computer aided diagnostics of prostate cancer. Prototype software was developed for the diagnostics of thyroid and breast cancers. This work was performed at the Advanced Medical Diagnostics SA in Belgium.